Posts Tagged ‘verilog’
PyParsing with Verilog
I came across this python parsing library called pyparsing through my adviser. The first thing I wanted to try implementing on this is a verilog parser. Actually, the site’ pages allows us to request a verilog parser from the author for non-commercial purposes. Anyways, thats not the point. I know and understand some verilog. So it makes more sense for me to try a verilog parser first. I have my parser for structural verilog using this module in my pbwiki page. It cannot handle many cases yet. But I took about an hour to get that code done. I spent about a day or two trying to figure out pyparsing itself. The documentation is fairly good. There are some interesting code snippets and howto in the pyparsing wiki page.
Now I am writing a full fledged verilog parser using this module. I’ve not requested for the author’s script yet. Maybe I’ll do that once I complete to figure out how good I am in using this library. And the full semantic/syntactic specification is available in IEEE explore and in Samir Palnitkar’s book on verilog HDL. I am not sure how much time I can devote to this, so it could be some time before I’ve followed this up. Meanwhile you might want to check the various samples in the pyparsing wiki.
